As integrated circuits continue to scale downward in size, the finFET is still an attractive device for use in semiconductor integrated circuits (ICs). With finFETs, as with other transistor types, contacts that connect to the source, drain, and gate of the transistor to other structure are an important factor in the production of reliable integrated circuits with desired performance characteristics. More specifically, source/drain (S/D) contact resistance is highly dependent on contact interface area. In conventional finFET devices, the contact area for S/D regions is the top of the S/D regions and is constant as the fin height increases. In advanced finFET devices, the contact area for S/D regions is the side of the S/D regions, thereby causing non-optimal drive current scaling as the fin height increases due to a small contact interface area. In other finFET devices, a partial wrap-around contact is formed on the top and sides of the S/D regions in an attempt to increase the contact interface area.
In the case of nanosheet-FETs, a particular type of finFETs, S/D epitaxy grows from the sides (edges) of the silicon layers (sheets) of the nanosheet stacks as well as the silicon substrate. Without isolation of the S/D contacts from the substrate, parasitic S/D leakage may occur which decreases nanosheet-FET performance.